1. Field of the Invention
This invention relates to a fabrication method of a trenched metal-oxide-semiconductor (MOS) device, and more particularly relates to a fabrication method of a high cell-density trenched MOS device.
2. Description of Related Art
The MOS devices can be sorted into the planar ones and the vertical ones according to the direction of current flow. For the planar MOS device, the source electrode and the drain electrode are located on the same surface of the semiconductor base to result in a horizontal conduction current, whereas, for the vertical MOS device, the source electrode and the drain electrode are located on the opposite surfaces of the semiconductor base respectively to result in a vertical conduction current.
As to the planar MOS device, the withstanding voltage depends on the length of the channel between the source electrode and the drain electrode, which is substantially identical to the width of the gate electrode. However, for the vertical MOS device, the withstanding voltage depends mainly on the doping concentration of the semiconductor base. Therefore, the planar MOS device usually needs to occupy a greater area on the semiconductor base and the increasing of cell density is thus restricted. In addition, according to the arrangement of gate electrode, the vertical MOS device can be sorted into the planar one and the trenched one. Wherein, the trenched-gate MOS device has the gate electrode arranged in a trench formed in the semiconductor base, which reduces the surface area occupied by the gate electrode and is helpful for increasing cell density.
FIG. 1 is a schematic view of a typical trenched-gate MOS device. As shown, the trenched-gate MOS device is formed on a semiconductor base 10, which is composed of a semiconductor substrate 12 and an epitaxial layer 14. The gate electrode 20 is located in a trench formed in the epitaxial layer 14 and is isolated from the epitaxial layer 14 with a gate oxide layer 22. The well 30 is located by the gate electrode 20. The source region 40 is located in the well 30. The source metal layer 60 connects the source region 40 and electrically couples to the well 30 through a heavily doped region 32.
In order to electrically isolate the gate electrode 20 from the source metal layer 60, an inter-layer dielectric layer 50 is formed over the gate electrode 20. The inter-layer dielectric layer 50 also has a contact window to expose the well 30 and the source region 40 so as to allow the source metal layer 60 on the inter-layer dielectric layer 50 contact the well region 30 and the source region 40.
The fabrication process of such trenched-gate MOS device needs at least three masks to define the location of gate electrode 20, the source region 40, and the contact window of the inter-layer dielectric layer 50, respectively. The alignment of each of the masks induces aligning errors. To prevent the failure of the MOS devices, the portion of the inter-layer dielectric layer 50 located on the gate electrode 20 should be wider than the gate electrode 20 plus a predetermined buffer to make sure that the source metal layer 60 is isolated from the gate electrode 20. Meanwhile, the range of the source region 40 should be great enough to make sure that the source region 40 is able to connect the source metal layer 60 through the inter-layer dielectric layer 50.
Therefore, the size of the MOS device is restricted not only by the minimum line-width of the lithographic process but also by the aligning errors among the aligning steps regarding each of the masks. For example, if there is an aligning error e1, e2 ranged from 0 to 0.1 micron, a buffer of 0.1 micron should be taken into concerned when the width of the inter-layer dielectric layer 50 or the source region 40 is estimated. That is, the MOS device has to preserve at least 0.4 micron as the buffer for the aligning errors.
Accordingly, it is an important issue to overcome the restriction of minimum line-width and aligning errors of the present semiconductor fabrication technology to find out a method to reduce the size of the MOS device so as to increase cell density.